The present disclosure relates generally to the design and use of micro-step resistance networks in high performance integrated circuits (ICs).
In Hard Disk Drive (HDD) servo IC design, accurate micro-step resistance networks are employed to help circuits meet both high performance and low IC area consumption requirements. Example HDD applications include Voice Coil Motor (VCM) current control loops and shock sensor resonance notch filters. In the VCM application they are used in a current sense amplifier to trim resistor accuracy in order to achieve a required Common Mode Rejection Ratio (CMRR). In the notch filter application they are used to tune the filter center frequency in order to cancel out a resonance tone caused by rotational vibration and generated at a shock sensor. The network resistance steps produced by micro-step resistance networks can be as small as a few ohms and the steps can be in a linear function, or they can follow other functions depending on the application.
Conventional systems will be described using FIG. 1 through FIG. 4.
FIG. 1 shows graph 100, which illustrates basic responses of a micro-step resistance network.
As shown in the figure, graph 100 includes an x-axis 102, a y-axis 104, a resistance value 106, a resistance value 108, a curve 110 and a curve 112.
X-axis 102 represents a resistance programming code, y-axis 104 represents resistance.
Curve 110 and curve 112 are both curves of micro-step resistance, adjustable in steps across a range of resistance values where resistance value 106 represents the minimum resistance (Rmin) and resistance value 108 represents the maximum resistance (Rmax) of the adjustment range, i.e., the adjustment range limits.
Curve 110 and curve 112 are adjustable by applying a resistance programming code to the micro-step network circuit, each programming code representing a resistance level. An example of a programming code is a simple sequence of binary codes such as 000, 001, 010, 011 . . . with each binary code applying a different resistance level.
It should be noted that curve 110 is a linear curve in which all the resistance level steps (i.e., the riser portions of the steps) are equal, while curve 112 is a non-linear curve where the steps are unequal.
FIG. 2 shows a conventional, basic, linear micro-step circuit 200.
As shown in the figure, circuit 200 includes an input 202, an output 204, a tapped resistor array 206, a tapped switch array 208, a resistor 210, a switch 212 and a head resistor 214.
Tapped resistor array 206 is arranged in series with head resistor 214 between input 202 and output 204. Tapped switch array 208 is arranged in parallel with tapped resistor array 206. The taps of tapped switch array 208 and tapped resistor array 206 are connected such that each individual switch is arranged in parallel with its corresponding individual resistor.
Tapped resistor array 206 contains 128 tapped resistors arranged in series. Tapped switch array 208 contains 128 tapped switches arranged in series.
Head resistor 214, resistor 210 and all other individual resistors of tapped resistor array 206 are operable to provide electrical resistance to a current. Switch 212 and all the other individual switches of tapped switch array 208 are operable to provide an electrical connection or disconnection depending on the closed (on) or open (off) state, respectively, of the switch.
In operation, the functions of resistor 210 and switch 212 should be assumed to be representative of other resistors and switches of the arrays. With switch 212 in the open state, the resistance R of resistor 210 is added to the total resistance between input 202 and output 204. With switch 212 closed, however, the resistance R of resistor 210 is not added to the total resistance between input 202 and output 204. Similarly, the resistance of any individual resistor of tapped resistor array 206 is added, or not added, to the total resistance between input 202 and output 204 depending on whether the resistor's corresponding switch (of tapped switch array 208) is in the open or closed state, respectively. For ideal switches, i.e., switches with on-state resistance (RSWon)=0Ω, the minimum resistance of the micro-step circuit, i.e., the minimum resistance between input 202 and output 204, is the resistance of head resistor 214 with all switches closed. The maximum resistance is the sum of all the resistors of tapped resistor array 206 plus the head resistor with all switches open. It should be noted that at any instant, the combined states of the all switches of tapped switch array 208 represents a resistance programming code such as the one referred to in FIG. 1.
In practice, the switches are not ideal and can have an appreciable RSWon value. This can significantly affect, adversely, the step accuracy of any micro-step resistance network. To minimize the inaccuracy, RSWon needs to be as small as possible and definitely much smaller than the nominal resistance value it is switching in or out of the circuit, e.g. RSWon of switch 212 needs to be much smaller than the resistance, R, of resistor 210 of FIG. 2. For instance, if R=100Ω for resistor 210, then, for a step accuracy of 10%, RSWon must be 10Ω or less for switch 212.
However, there is a trade off in the size of circuit real-estate to RSWon. For example, if an NMOS device and a PMOS device (each with 20Ω) are tied in parallel to form a transmission gate switch of RSWon=10Ω, and assuming the voltage driving the MOS gates is 1.8V, the threshold voltage VT is 0.5V, the signal level Vs passing through the switch is 0.9V and device length Ln=0.2 μm, then:
                              R          SWON_NMOS                =                              1                                                            K                  n                  ′                                ⁡                                  (                                                            W                      n                                        /                                          L                      n                                                        )                                            ×                              (                                                      V                    G                                    -                                      V                    S                                    -                                      V                    T                                                  )                                              =                                    1                              160                ×                                  10                                      -                    6                                                  ×                                  (                                                            W                      n                                        /                                          L                      n                                                        )                                ×                                  (                                      1.8                    -                    0.9                    -                    0.5                                    )                                                      ≤                          20              ⁢              Ω                                                          (        1        )            The above calculation results in a physical NMOS device width Wn=156.25 μm. Since for PMOS, K″p is about four times smaller than that of NMOS (K′n), then the PMOS device will have a 4× larger size, i.e., Wp=625 m.
It should be noted that in equation (1), the NMOS on-state resistance is a function of K′n which is proportional to the semiconductor carrier mobility, and typically becomes 2× smaller when the circuit temperature is raised from room temperature (27° C.) to 1250° C. In addition, the device threshold Vth also varies with temperature. These temperature effects affecting RSWon are defined as temperature coefficients (TCs). The NMOS on-state resistance is also a function of the signal level (Vs) passing through the switch, which is assumed to be fixed 0.9V in equation (1) for simplicity of the calculation. However, in practice Vs may vary from 0V to 1.8V (in a transmission gate switch, NMOS device work for Vs ranges from 0V to 1.8-Vth=1.3V and PMOS device works for Vs ranges from Vth=0.5V to Vdd=1.8V). To ensure the micro-step network accurately works over a certain temperature range and a certain signal level range, i.e., that it overcomes temperature coefficients and voltage coefficients, the actual switch size may need to be 4× larger than that the size calculated in equation (1), i.e., Wn=625 um and Wp=2500 um. Such large sizes are not acceptable in high-volume low-cost IC design.
Other conventional micro-step resistor network implementations will now discussed with reference to FIGS. 3-4.
FIG. 3 shows a first alternate example of a conventional micro-step resistance network circuit 300.
As shown in the figure, circuit 300 includes input 202, output 204, tapped resistor array 206, resistor 210, switch 212, head resistor 214, a switch 302, a switch array 304, a switch 306 and a switch 308.
Switch 302 is arranged in parallel with resistor 210 and the second resistor of tapped resistor array 206. This arrangement pattern, i.e., a switch arranged between output 204 and each of the resistors of tapped resistor array 206 is repeated for all switches in switch array 304. At the end of the pattern sequence, switch 306 is arranged in parallel with resistor 210 and all the resistors of tapped resistor array 206 except the last one, and switch 308 is arranged in parallel with resistor 210 and all the resistors of tapped resistor array 206.
Tapped resistor array 206 contains 128 tapped resistors arranged in series. Switch array 306 contains 124 switches and so with switch 212, switch 302, switch 304 and switch 306 there are a total of 128 switches.
Switch 212, switch 306, switch 308 and all the other individual switches of switch array 304 are operable to provide an electrical connection or disconnection depending on the closed or open state (respectively) of the switch.
In operation, circuit 300 differs from circuit 200 of FIG. 2 in that each switch controls the insertion or non-insertion of a different number of resistors each of value R, into the total resistance between input 202 and output 204. This means that for any of the possible values of total resistance only one switch need be closed.
It should be noted that for circuit 300, the least significant switches (those that switch the fewer number of resistors of tapped resistor array 206) the RSWon and therefore the switch size problem remains as for circuit 200. However, for the most significant switches, the problem is relieved somewhat due to the larger difference between RSWon and the resistance being switched.
FIG. 4 shows a second alternate example of a conventional micro-step resistance network circuit 400.
As shown in the figure, circuit 400 includes input 202, output 204, a tapped resistor array 402, a tapped switch array 404, resistor 210, switch 212 and head resistor 214.
Tapped resistor array 402 is arranged in series with head resistor 214 between input 202 and output 204. Tapped switch array 404 is arranged in parallel with tapped resistor array 402. The taps of tapped switch array 404 and tapped resistor array 402 are connected such that each individual switch is arranged in parallel with its corresponding individual resistor.
Head resistor 214, resistor 210 and all other individual resistors of tapped resistor array 402 are operable to provide electrical resistance to a current. Switch 212 and all the other individual switches of tapped switch array 404 are operable to provide an electrical connection or disconnection depending on the closed or open state (respectively) of the switch.
It can be seen that circuit 400 is very similar in arrangement to circuit 200 of FIG. 2. The difference is in the resistance values of the individual resistors of the tapped resistor arrays. Rather than being all of the same value as in tapped resistor array 206, the values within tapped resistor array 402 follow a binary scaled progression from output to input as shown. Operation of the two circuits is also similar.
As for circuit 400 of FIG. 4, there can be a size problem for the least significant switches towards the output end of circuit 400, while at the input end, this problem is relieved for the most significant switches due the larger resistances being switched.
The circuits described so far have been series resistance circuits. In some applications, parallel resistance circuits are used for micro-step resistor networks. This will be described in greater detail with reference to FIGS. 5A-B.
FIG. 5A shows a conventional 3-bit parallel micro-step resistor network circuit 500.
As shown in the figure, circuit 500 includes input 202, output 204, a resistor 502, a resistor array 503 and a switch array 509. Resistor array includes a resistor 504, a resistor 506 and a resistor 508. Switch array 509 includes a switch 510, a switch 512 and a switch 514.
Resistor 502, resistor 504 resistor 506 and resistor 508 are arranged in parallel with each other between input 202 and output 204. Switch 510 is arranged between resistor 504 and input 202, switch 512 is arranged between resistor 506 and input 202, and switch 514 is arranged between resistor 504 and input 202.
Resistors 502, 504, 506 and 508 are operable to provide electrical resistance to a current. Switches 510, 512 and 514 are operable to provide an electrical connection or disconnection depending on the closed or open state (respectively) of the switch.
In operation, a programming code 516, which is a 3-bit code (b0, b1, b2), is applied to switches 510, 512 and 514 controls their states to allow resistors 504, 506 and 508 respectively to contribute (or not) to the overall circuit resistance between input 202 and output 204. Since resistors are in parallel, R0 is the maximum overall resistance limit with all switches open, the overall resistance reduces as resistances are switched in (switch closures) and the minimum overall resistance of the circuit is attained when all switches are closed.
An advantage of the parallel structure network is that small steps can be achieved with large resistance values, so when compared with series structures, RSWon and the corresponding switch size issues are greatly relieved. However, the main disadvantage of a parallel structure network is that the curve produced can be non-linear, i.e., there are variations in step size. This will be explained using a smaller micro-step resistor network using a 2-bit code.
FIG. 5B shows a conventional 2-bit parallel micro-step resistor network circuit 501.
As shown in the figure, circuit 501 includes resistor 502, resistor 504, resistor 506, a switch 510 and switch 512.
All components of circuit 501 are arranged and are operable as described for circuit 500 of FIG. 5A.
Circuit 501 is a modified version of circuit 500 with the last parallel resistor and switch removed, and, while it has a fewer number of branches, it operates in the same manner as circuit 500 but uses a 2-bit programming code (515) instead of a 3-bit programming code (516). The non-linear steps of the parallel-structure can be seen from the following equation which represents the circuit:
                                          R            effective                    ⁡                      [                          b              ⁢                                                          ⁢              1              ⁢              b              ⁢                                                          ⁢              0                        ]                          =                  1                                    1                              R                ⁢                                                                  ⁢                0                                      +                          b              ⁢                                                          ⁢              1              ×                              1                                  R                  ⁢                                                                          ⁢                  1                                                      +                          b              ⁢                                                          ⁢              0              ×                              1                                  R                  ⁢                                                                          ⁢                  2                                                                                        (        2        )            where programming codes applied to [b1b0]=00, 01, 10, 11. While the denominator portion of equation (2) increments linearly, the steps of Reffective, are non-linear. For example, if R0=1 kΩ, R1=50 kΩ and R2=100 kΩ, then the step from Reffective [b1b0]=00 to Reffective [b1b0]=01 is 10Ω, while the step from Reffective [b1b0]=01 to Reffective [b1b0]=11 is 9.1Ω, a 10% difference.
Conventional implementations of series-structure micro-step resistance networks in integrated circuits are subject to a trade-off between large inaccuracies in step size on the one hand and large switch implementation sizes on the other. This is due to the inverse relationship between switch on-resistance and physical switch size and that this problem is further exacerbated when the operational ranges of temperature and voltage are taken into account due to the large effect of temperature and voltage coefficients.
While parallel structure micro-step networks can go a long way towards mitigating such problems, large variations in step size due to the non-linear response of these structures then becomes a significant implementation disadvantage.
What is needed are systems and methods which can be used to implement accurate micro-step series resistance networks without the size problems of conventional implementations as well as systems and methods which can implement parallel micro-step resistor networks which significantly reduce the variation in step size caused by the conventional parallel structure's non-linear response.